{"id":"CVE-2020-0574","aliases":["EUVD-2020-2072","GHSA-q9j8-mc5q-47m3"],"status":"published","title":"Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an...","description":"Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.","severity":{"version":"3.1","score":5.9,"vector":"CVSS:3.1/AV:P/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:N","level":"medium","assessor":"primary","from":"nvd"},"epss":{"day":"2026-11-10","score":0.00364,"percentile":0.30513,"model":"v2026.06.15"},"facts":{"in_kev":false,"known_exploited":false,"public_exploit":false,"fix_available":false},"cwes":["CWE-200"],"published":"2020-03-12T20:52:29Z","modified":"2026-06-17T02:46:05Z","products":[{"vendor":"intel","product":"intel(r) max(r) 10 fpga"},{"vendor":"intel","product":"max_10_fpga_firmware"}],"references":[{"url":"https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00349.html","tags":["x_refsource_CONFIRM","x_transferred","Vendor Advisory"]},{"url":"https://nvd.nist.gov/vuln/detail/CVE-2020-0574"},{"url":"https://github.com/advisories/GHSA-q9j8-mc5q-47m3"}],"sources":{"cve":[{"id":"CVE-2020-0574","description":"Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.","status":"published","published":"2020-03-12T20:52:29Z","modified":"2024-08-04T06:02:52.194Z","updated_at":"2026-11-02T14:35:59.763887Z"}],"euvd":[{"id":"EUVD-2020-2072","description":"Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.","status":"published","published":"2020-03-12T20:52:29Z","modified":"2024-08-04T06:02:52Z","updated_at":"2026-11-03T03:08:19.102243Z"}],"ghsa":[{"id":"GHSA-q9j8-mc5q-47m3","title":"Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an...","description":"Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable information disclosure via physical access.","status":"published","published":"2022-05-24T17:10:53Z","modified":"2023-01-29T05:01:49Z","cwes":["CWE-200"],"updated_at":"2026-11-02T14:44:55.382004Z"}],"nvd":[{"id":"CVE-2020-0574","description":"Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.","status":"published","published":"2020-03-12T21:15:14.373Z","modified":"2026-06-17T02:46:05.553Z","cvss":[{"version":"3.1","score":5.9,"vector":"CVSS:3.1/AV:P/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:N","level":"medium","assessor":"primary"},{"version":"2.0","score":3.6,"vector":"AV:L/AC:L/Au:N/C:P/I:P/A:N","level":"low","assessor":"primary"}],"updated_at":"2026-11-02T14:05:55.32877Z"}]}}