{"id":"CVE-2021-1104","aliases":["EUVD-2021-6571","GHSA-5pxp-m22f-2m9x"],"status":"published","title":"The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector...","description":"The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.","severity":{"version":"3.1","score":9.8,"vector":"CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H","level":"critical","assessor":"primary","from":"nvd"},"epss":{"day":"2026-11-10","score":0.01663,"percentile":0.76907,"model":"v2026.06.15"},"facts":{"in_kev":false,"known_exploited":false,"public_exploit":false,"fix_available":false},"cwes":["CWE-908"],"published":"2021-08-13T15:40:51Z","modified":"2026-06-17T03:30:58Z","products":[{"vendor":"risc-v","product":"instruction_set_manual"},{"vendor":"riscv.org","product":"machine trap base address (mtvec) register"}],"references":[{"url":"https://riscv.org/news/2021/08/video-glitching-risc-v-chips-mtvec-corruption-for-hardening-isa-adam-zabrocki-and-alex-matrosov-def-con-29/","tags":["x_refsource_CONFIRM","x_transferred","Exploit","Vendor Advisory"]},{"url":"https://nvd.nist.gov/vuln/detail/CVE-2021-1104"},{"url":"https://github.com/advisories/GHSA-5pxp-m22f-2m9x"}],"sources":{"cve":[{"id":"CVE-2021-1104","description":"The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.","status":"published","published":"2021-08-13T15:40:51Z","modified":"2024-08-03T15:55:18.614Z","updated_at":"2026-11-02T14:33:08.811269Z"}],"euvd":[{"id":"EUVD-2021-6571","description":"The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.","status":"published","published":"2021-08-13T15:40:51Z","modified":"2024-08-03T15:55:18Z","updated_at":"2026-11-03T03:25:15.150715Z"}],"ghsa":[{"id":"GHSA-5pxp-m22f-2m9x","title":"The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector...","description":"The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.","status":"published","published":"2022-05-24T19:11:05Z","modified":"2023-01-30T05:01:33Z","cwes":["CWE-908"],"updated_at":"2026-11-02T14:46:25.989719Z"}],"nvd":[{"id":"CVE-2021-1104","description":"The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address (MTVEC) register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of service.","status":"published","published":"2021-08-13T16:15:07.153Z","modified":"2026-06-17T03:30:58.07Z","cvss":[{"version":"3.1","score":9.8,"vector":"CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:H/A:H","level":"critical","assessor":"primary"},{"version":"2.0","score":7.5,"vector":"AV:N/AC:L/Au:N/C:P/I:P/A:P","level":"high","assessor":"primary"}],"cwes":["CWE-908"],"updated_at":"2026-11-02T14:06:56.943671Z"}]}}