{"id":"CVE-2025-31648","aliases":["ALPINE-CVE-2025-31648","BELL-CVE-2025-31648","DEBIAN-CVE-2025-31648","EUVD-2025-207126","GHSA-cf43-7r7r-9f4f","MGASA-2026-0043","OESA-2026-1418","OESA-2026-1419","OESA-2026-1420","OESA-2026-1421","OESA-2026-1422","OESA-2026-1440","SUSE-SU-2026:0668-1","SUSE-SU-2026:0669-1","SUSE-SU-2026:0670-1","SUSE-SU-2026:20522-1","SUSE-SU-2026:20682-1","SUSE-SU-2026:20758-1","SUSE-SU-2026:20941-1","UBUNTU-CVE-2025-31648","USN-8068-1","openSUSE-SU-2026:10229-1","openSUSE-SU-2026:20401-1"],"status":"published","title":"Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an...","description":"Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.","severity":{"version":"4.0","score":1.8,"vector":"CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:L/VI:L/VA:N/SC:L/SI:L/SA:N","level":"low","assessor":"cna","from":"cve"},"epss":{"day":"2026-11-11","score":0.00149,"percentile":0.04111,"model":"v2026.06.15"},"facts":{"in_kev":false,"known_exploited":false,"public_exploit":false,"fix_available":true},"cwes":["CWE-229"],"published":"2026-02-10T16:25:36Z","modified":"2026-09-01T20:05:45Z","fixes":[{"ecosystem":"Alpine:v3.20","package":"intel-ucode","fixed_in":["20260210-r0"],"sources":["osv"]},{"ecosystem":"Alpine:v3.21","package":"intel-ucode","fixed_in":["20260210-r0"],"sources":["osv"]},{"ecosystem":"Alpine:v3.22","package":"intel-ucode","fixed_in":["20260210-r0"],"sources":["osv"]},{"ecosystem":"Alpine:v3.23","package":"intel-ucode","fixed_in":["20260210-r0"],"sources":["osv"]},{"ecosystem":"Alpine:v3.24","package":"intel-ucode","fixed_in":["20260210-r0"],"sources":["osv"]},{"ecosystem":"Alpaquita:23","package":"intel-ucode","fixed_in":["20260210-r0"],"sources":["osv"]},{"ecosystem":"Alpaquita:25","package":"intel-ucode","fixed_in":["20260210-r0"],"sources":["osv"]},{"ecosystem":"Alpaquita:stream","package":"intel-ucode","fixed_in":["20260210-r0"],"sources":["osv"]},{"ecosystem":"Debian:14","package":"intel-microcode","fixed_in":["3.20260210.1"],"sources":["osv"]},{"ecosystem":"openEuler:24.03-LTS-SP1","package":"microcode_ctl","fixed_in":["20260210.1-1.oe2403sp1"],"sources":["osv"]},{"ecosystem":"openEuler:24.03-LTS-SP2","package":"microcode_ctl","fixed_in":["20260210.1-1.oe2403sp2"],"sources":["osv"]},{"ecosystem":"openEuler:24.03-LTS-SP3","package":"microcode_ctl","fixed_in":["20260210.1-1.oe2403sp3"],"sources":["osv"]},{"ecosystem":"openEuler:22.03-LTS-SP4","package":"microcode_ctl","fixed_in":["20260210.1-1.oe2203sp4"],"sources":["osv"]},{"ecosystem":"openEuler:24.03-LTS","package":"microcode_ctl","fixed_in":["20260210.1-1.oe2403"],"sources":["osv"]},{"ecosystem":"openEuler:20.03-LTS-SP4","package":"microcode_ctl","fixed_in":["20260210.1-1.oe2003sp4"],"sources":["osv"]},{"ecosystem":"Ubuntu:Pro:16.04:LTS","package":"intel-microcode","fixed_in":["3.20260210.0ubuntu0.16.04.1+esm1"],"sources":["osv"]},{"ecosystem":"Ubuntu:Pro:18.04:LTS","package":"intel-microcode","fixed_in":["3.20260210.0ubuntu0.18.04.1+esm1"],"sources":["osv"]},{"ecosystem":"Ubuntu:Pro:20.04:LTS","package":"intel-microcode","fixed_in":["3.20260210.0ubuntu0.20.04.1+esm1"],"sources":["osv"]},{"ecosystem":"Ubuntu:22.04:LTS","package":"intel-microcode","fixed_in":["3.20260210.0ubuntu0.22.04.1"],"sources":["osv"]},{"ecosystem":"Ubuntu:24.04:LTS","package":"intel-microcode","fixed_in":["3.20260210.0ubuntu0.24.04.1"],"sources":["osv"]},{"ecosystem":"Ubuntu:25.10","package":"intel-microcode","fixed_in":["3.20260210.0ubuntu0.25.10.1"],"sources":["osv"]},{"ecosystem":"openSUSE:Tumbleweed","package":"ucode-intel","fixed_in":["20260210-1.1"],"sources":["osv"]}],"affected":[{"source":"osv","ecosystem":"Alpine:v3.20","package":"intel-ucode","ranges":[{"type":"ECOSYSTEM","events":[{"introduced":"0"},{"fixed":"20260210-r0"}]}]},{"source":"osv","ecosystem":"Alpine:v3.21","package":"intel-ucode","ranges":[{"type":"ECOSYSTEM","events":[{"introduced":"0"},{"fixed":"20260210-r0"}]}]},{"source":"osv","ecosystem":"Alpine:v3.22","package":"intel-ucode","ranges":[{"type":"ECOSYSTEM","events":[{"introduced":"0"},{"fixed":"20260210-r0"}]}]},{"source":"osv","ecosystem":"Alpine:v3.23","package":"intel-ucode","ranges":[{"type":"ECOSYSTEM","events":[{"introduced":"0"},{"fixed":"20260210-r0"}]}]},{"source":"osv","ecosystem":"Alpine:v3.24","package":"intel-ucode","ranges":[{"type":"ECOSYSTEM","events":[{"introduced":"0"},{"fixed":"20260210-r0"}]}]},{"source":"osv","ecosystem":"Alpaquita:23","package":"intel-ucode","ranges":[{"type":"ECOSYSTEM","events":[{"introduced":"20230516a-r0"},{"fixed":"20260210-r0"}]}]},{"source":"osv","ecosystem":"Alpaquita:25","package":"intel-ucode","ranges":[{"type":"ECOSYSTEM","events":[{"introduced":"20250512-r0"},{"fixed":"20260210-r0"}]}]},{"source":"osv","ecosystem":"Alpaquita:stream","package":"intel-ucode","ranges":[{"type":"ECOSYSTEM","events":[{"introduced":"20230214-r0"},{"fixed":"20260210-r0"}]}]},{"source":"osv","ecosystem":"Debian:12","package":"intel-microcode","ranges":[{"type":"ECOSYSTEM","events":[{"introduced":"0"}]}],"versions":["0.20080131-1","0.20080220-1","0.20080401-1","0.20080910-1","0.20080910-2","0.20090330-1","0.20090927-1","0.20100826-1","0.20100914-1","0.20101123-1","0.20110428-1","0.20110915-1","0.20111110-1","0.20120606-1","1.20120606.1","1.20120606.2","1.20120606.3","1.20120606.4","1.20120606.5","1.20120606.6","1.20120606.6~bpo60+1","1.20120606.v2.1","1.20120606.v2.2","1.20120606.v2.2~bpo60+1","1.20130222.1","1.20130222.1~bpo60+1","1.20130222.3","1.20130222.4","1.20130222.5","1.20130222.6","1.20130808.1","1.20130808.2","1.20130906.1","1.20140122.1","1.20140122.1~bpo60+1","1.20140430.1","1.20140430.1~bpo60+1","1.20140624.1","1.20140624.1~bpo60+1","1.20140913.1",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handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.","status":"published","published":"2026-02-10T16:25:36.35Z","modified":"2026-02-26T15:04:09.683Z","cvss":[{"version":"4.0","score":1.8,"vector":"CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:L/VI:L/VA:N/SC:L/SI:L/SA:N","level":"low","assessor":"cna"},{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low","assessor":"cna"}],"cwes":["CWE-229"],"updated_at":"2026-11-02T14:32:44.424933Z"}],"euvd":[{"id":"EUVD-2025-207126","description":"Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.","status":"published","published":"2026-02-10T16:25:36Z","modified":"2026-02-26T15:04:09Z","cvss":[{"version":"4.0","score":1.8,"vector":"CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:L/VI:L/VA:N/SC:L/SI:L/SA:N","level":"low"}],"updated_at":"2026-11-02T19:48:27.038974Z"}],"ghsa":[{"id":"GHSA-cf43-7r7r-9f4f","title":"Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an...","description":"Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.","status":"published","published":"2026-02-10T18:30:40Z","modified":"2026-02-10T18:30:49Z","cvss":[{"version":"4.0","score":1.8,"vector":"CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:L/VI:L/VA:N/SC:L/SI:L/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X","level":"low"},{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low"}],"cwes":["CWE-229"],"updated_at":"2026-11-02T15:06:07.875228Z"}],"nvd":[{"id":"CVE-2025-31648","description":"Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.","status":"published","published":"2026-02-10T17:16:15.55Z","modified":"2026-06-17T09:10:43.757Z","cvss":[{"version":"4.0","score":1.8,"vector":"CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:L/VI:L/VA:N/SC:L/SI:L/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X","level":"low","assessor":"secondary"},{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low","assessor":"secondary"}],"cwes":["CWE-229"],"updated_at":"2026-11-02T14:11:59.832225Z"}],"osv":[{"id":"ALPINE-CVE-2025-31648","description":"Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.","status":"published","published":"2026-02-10T17:16:15.55Z","modified":"2026-08-27T22:18:02.880786495Z","cvss":[{"version":"4.0","score":1.8,"vector":"CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:L/VI:L/VA:N/SC:L/SI:L/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X","level":"low"}],"updated_at":"2026-11-02T15:27:50.269992Z"},{"id":"BELL-CVE-2025-31648","status":"published","published":"2026-02-14T06:08:44.628487Z","modified":"2026-02-19T07:15:26.500751Z","cvss":[{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low"}],"updated_at":"2026-11-02T15:28:21.741325Z"},{"id":"DEBIAN-CVE-2025-31648","description":"Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.","status":"published","published":"2026-02-10T17:16:15.55Z","modified":"2026-09-01T20:05:45.817523825Z","cvss":[{"version":"4.0","score":1.8,"vector":"CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:L/VI:L/VA:N/SC:L/SI:L/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X","level":"low"}],"updated_at":"2026-11-02T15:45:45.870237Z"},{"id":"OESA-2026-1418","title":"microcode_ctl security update","description":"This is a tool to transform and deploy microcode update for x86 CPUs.\r\n\r\nSecurity Fix(es):\n\nImproper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.(CVE-2025-31648)","status":"published","published":"2026-02-13T11:10:26Z","modified":"2026-08-18T01:19:55.267128754Z","cvss":[{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low"}],"updated_at":"2026-11-02T15:52:45.721983Z"},{"id":"OESA-2026-1419","title":"microcode_ctl security update","description":"This is a tool to transform and deploy microcode update for x86 CPUs.\r\n\r\nSecurity Fix(es):\n\nImproper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.(CVE-2025-31648)","status":"published","published":"2026-02-13T11:10:26Z","modified":"2026-08-18T01:19:55.276493195Z","cvss":[{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low"}],"updated_at":"2026-11-02T15:52:45.721983Z"},{"id":"OESA-2026-1420","title":"microcode_ctl security update","description":"This is a tool to transform and deploy microcode update for x86 CPUs.\r\n\r\nSecurity Fix(es):\n\nImproper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.(CVE-2025-31648)","status":"published","published":"2026-02-13T11:10:26Z","modified":"2026-08-18T01:19:40.248847608Z","cvss":[{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low"}],"updated_at":"2026-11-02T15:52:45.721983Z"},{"id":"OESA-2026-1421","title":"microcode_ctl security update","description":"This is a tool to transform and deploy microcode update for x86 CPUs.\r\n\r\nSecurity Fix(es):\n\nImproper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.(CVE-2025-31648)","status":"published","published":"2026-02-13T11:10:26Z","modified":"2026-08-18T01:19:33.751790452Z","cvss":[{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low"}],"updated_at":"2026-11-02T15:52:45.721983Z"},{"id":"OESA-2026-1422","title":"microcode_ctl security update","description":"This is a tool to transform and deploy microcode update for x86 CPUs.\r\n\r\nSecurity Fix(es):\n\nImproper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.(CVE-2025-31648)","status":"published","published":"2026-02-13T11:10:26Z","modified":"2026-08-18T01:19:40.237849882Z","cvss":[{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low"}],"updated_at":"2026-11-02T15:52:45.721983Z"},{"id":"OESA-2026-1440","title":"microcode_ctl security update","description":"This is a tool to transform and deploy microcode update for x86 CPUs.\r\n\r\nSecurity Fix(es):\n\nImproper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.(CVE-2025-31648)","status":"published","published":"2026-02-28T11:10:27Z","modified":"2026-08-18T01:19:33.966690347Z","cvss":[{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low"}],"updated_at":"2026-11-02T15:52:45.721983Z"},{"id":"UBUNTU-CVE-2025-31648","description":"Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an escalation of privilege. Startup code and smm adversary with a privileged user combined with a high complexity attack may enable escalation of privilege. This result may potentially occur via local access when attack requirements are present with special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (low), integrity (low) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (low), integrity (low) and availability (none) impacts.","status":"published","published":"2026-02-10T17:16:00Z","modified":"2026-03-04T08:02:48.565107Z","cvss":[{"version":"3.1","score":3.9,"vector":"CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:L/I:L/A:N","level":"low"},{"version":"4.0","score":1.8,"vector":"CVSS:4.0/AV:L/AC:H/AT:P/PR:H/UI:N/VC:L/VI:L/VA:N/SC:L/SI:L/SA:N","level":"low"}],"updated_at":"2026-11-02T16:55:28.829873Z"},{"id":"MGASA-2026-0043","title":"Updated microcode packages fix security vulnerabilities","description":"The updated package updates AMD CPUs microcodes and fixes security\nvulnerabilities in Intel CPUs microcodes:\nIncorrect behavior order in transition between executive monitor and SMI\ntransfer monitor (STM) in some Intel(R) Processor may allow a privileged\nuser to potentially enable escalation of privilege via local access.\n(CVE-2024-24853)\nImproper handling of values in the microcode flow for some Intel(R)\nProcessor Family may allow an escalation of privilege. Startup code and\nsmm adversary with a privileged user combined with a high complexity\nattack may enable escalation of privilege. This result may potentially\noccur via local access when attack requirements are present with special\ninternal knowledge and requires no user interaction. The potential\nvulnerability may impact the confidentiality (low), integrity (low) and\navailability (none) of the vulnerable system, resulting in subsequent\nsystem confidentiality (low), integrity (low) and availability (none)\nimpacts. (CVE-2025-31648)\n","status":"published","published":"2026-02-18T16:17:22Z","modified":"2026-04-16T04:41:39.328263195Z","updated_at":"2026-11-02T15:49:43.178336Z"},{"id":"openSUSE-SU-2026:10229-1","title":"ucode-intel-20260210-1.1 on GA media","description":"These are all security issues fixed in the ucode-intel-20260210-1.1 package on the GA media of openSUSE Tumbleweed.","status":"published","published":"2026-02-19T00:00:00Z","modified":"2026-03-23T04:54:35.342539Z","updated_at":"2026-11-02T16:58:38.101535Z"},{"id":"openSUSE-SU-2026:20401-1","title":"Security update for ucode-intel","description":"This update for ucode-intel fixes the following issues:\n\n- Intel CPU Microcode was updated to the 20260210 release (bsc#1258046):\n\n  - CVE-2024-24853: Updated fix for incorrect behavior order in transition\n    between executive monitor and SMI transfer monitor (STM) in some Intel(R)\n    Processor may allow a privileged user to potentially enable escalation\n    of privilege via local access (bsc#1229129).\n\n  - CVE-2025-31648: Improper handling of values in the\n    microcode flow for some Intel Processor Family may allow\n    an escalation of privilege (bsc#1258046).\n\n- Intel CPU Microcode was updated to the 20251111 release (bsc#1253319):\n\n  - Update for functional issues.\n\n- switch the supplements to use supplements + kernel to allow\n  moving a installation to Intel hardware (bsc#1249138)\n\n- Intel CPU Microcode was updated to the 20241029 release (bsc#1230400):\n\n  - Update for functional issues.\n","status":"published","published":"2026-03-19T09:31:38Z","modified":"2026-03-29T17:24:12.830443Z","updated_at":"2026-11-02T16:58:41.463445Z"},{"id":"SUSE-SU-2026:0668-1","title":"Security update for ucode-intel","description":"This update for ucode-intel fixes the following issues:\n\n- Intel CPU Microcode was updated to the 20260210 release (bsc#1258046)\n- CVE-2024-24853: Updated fix for incorrect behavior order in transition\n  between executive monitor and SMI transfer monitor (STM) in some Intel(R)\n  Processor may allow a privileged user to potentially enable escalation\n  of privilege via local access. (bsc#1229129)\n- CVE-2025-31648: Improper handling of values in the microcode flow for\n  some Intel Processor Family may allow an escalation of privilege. (bsc#1258046)\n","status":"published","published":"2026-02-26T15:21:13Z","modified":"2026-03-23T04:52:25.192826Z","updated_at":"2026-11-02T15:54:01.262144Z"},{"id":"SUSE-SU-2026:0669-1","title":"Security update for ucode-intel","description":"This update for ucode-intel fixes the following issues:\n\n- Intel CPU Microcode was updated to the 20260210 release (bsc#1258046)\n- CVE-2024-24853: Updated fix for incorrect behavior order in transition\n  between executive monitor and SMI transfer monitor (STM) in some Intel(R)\n  Processor may allow a privileged user to potentially enable escalation\n  of privilege via local access. (bsc#1229129)\n- CVE-2025-31648: Improper handling of values in the microcode flow for\n  some Intel Processor Family may allow an escalation of privilege. (bsc#1258046)\n","status":"published","published":"2026-02-26T15:21:31Z","modified":"2026-03-23T04:52:24.96462Z","updated_at":"2026-11-02T15:54:01.262144Z"},{"id":"SUSE-SU-2026:0670-1","title":"Security update for ucode-intel","description":"This update for ucode-intel fixes the following issues:\n\n- Intel CPU Microcode was updated to the 20260210 release (bsc#1258046)\n- CVE-2024-24853: Updated fix for incorrect behavior order in transition\n  between executive monitor and SMI transfer monitor (STM) in some Intel(R)\n  Processor may allow a privileged user to potentially enable escalation\n  of privilege via local access. (bsc#1229129)\n- CVE-2025-31648: Improper handling of values in the microcode flow for\n  some Intel Processor Family may allow an escalation of privilege. (bsc#1258046)\n","status":"published","published":"2026-02-26T15:21:41Z","modified":"2026-03-23T04:52:25.730917Z","updated_at":"2026-11-02T15:54:01.262144Z"},{"id":"SUSE-SU-2026:20522-1","title":"Security update for ucode-intel","description":"This update for ucode-intel fixes the following issues:\n\n- Intel CPU Microcode was updated to the 20260210 release (bsc#1258046):\n\n  - CVE-2024-24853: Updated fix for incorrect behavior order in transition\n    between executive monitor and SMI transfer monitor (STM) in some Intel(R)\n    Processor may allow a privileged user to potentially enable escalation\n    of privilege via local access (bsc#1229129).\n\n  - CVE-2025-31648: Improper handling of values in the\n    microcode flow for some Intel Processor Family may allow\n    an escalation of privilege (bsc#1258046).\n","status":"published","published":"2026-02-26T10:48:45Z","modified":"2026-03-23T04:53:01.690082Z","updated_at":"2026-11-02T15:54:01.953589Z"},{"id":"SUSE-SU-2026:20682-1","title":"Security update for ucode-intel","description":"This update for ucode-intel fixes the following issues:\n\n- Intel CPU Microcode was updated to the 20260210 release (bsc#1258046):\n\n  - CVE-2024-24853: Updated fix for incorrect behavior order in transition\n    between executive monitor and SMI transfer monitor (STM) in some Intel(R)\n    Processor may allow a privileged user to potentially enable escalation\n    of privilege via local access (bsc#1229129).\n\n  - CVE-2025-31648: Improper handling of values in the\n    microcode flow for some Intel Processor Family may allow\n    an escalation of privilege (bsc#1258046).\n","status":"published","published":"2026-03-06T13:29:07Z","modified":"2026-03-23T04:53:08.230557Z","updated_at":"2026-11-02T15:54:01.953589Z"},{"id":"SUSE-SU-2026:20758-1","title":"Security update for ucode-intel","description":"This update for ucode-intel fixes the following issues:\n\n- Intel CPU Microcode was updated to the 20260210 release (bsc#1258046):\n\n  - CVE-2024-24853: Updated fix for incorrect behavior order in transition\n    between executive monitor and SMI transfer monitor (STM) in some Intel(R)\n    Processor may allow a privileged user to potentially enable escalation\n    of privilege via local access (bsc#1229129).\n\n  - CVE-2025-31648: Improper handling of values in the\n    microcode flow for some Intel Processor Family may allow\n    an escalation of privilege (bsc#1258046).\n\n- Intel CPU Microcode was updated to the 20251111 release (bsc#1253319):\n\n  - Update for functional issues.\n\n- switch the supplements to use supplements + kernel to allow\n  moving a installation to Intel hardware (bsc#1249138)\n\n- Intel CPU Microcode was updated to the 20241029 release (bsc#1230400):\n\n  - Update for functional issues.\n","status":"published","published":"2026-03-19T09:31:38Z","modified":"2026-03-25T17:23:42.806433Z","updated_at":"2026-11-02T15:54:01.953589Z"},{"id":"SUSE-SU-2026:20941-1","title":"Security update for ucode-intel","description":"This update for ucode-intel fixes the following issues:\n\n- Intel CPU Microcode was updated to the 20260210 release (bsc#1258046):\n\n  - CVE-2024-24853: Updated fix for incorrect behavior order in transition\n    between executive monitor and SMI transfer monitor (STM) in some Intel(R)\n    Processor may allow a privileged user to potentially enable escalation\n    of privilege via local access (bsc#1229129).\n\n  - CVE-2025-31648: Improper handling of values in the\n    microcode flow for some Intel Processor Family may allow\n    an escalation of privilege (bsc#1258046).\n\n- Intel CPU Microcode was updated to the 20251111 release (bsc#1253319):\n\n  - Update for functional issues.\n\n- switch the supplements to use supplements + kernel to allow\n  moving a installation to Intel hardware (bsc#1249138)\n\n- Intel CPU Microcode was updated to the 20241029 release (bsc#1230400):\n\n  - Update for functional issues.\n","status":"published","published":"2026-03-19T09:31:38Z","modified":"2026-04-02T17:25:00.73211Z","updated_at":"2026-11-02T15:54:01.953589Z"},{"id":"USN-8068-1","title":"intel-microcode vulnerability","description":"Sergiu Ghetie discovered that some Intel® processors did not properly\nhandle values in the microcode flow. A local authenticated user could\npotentially use this issue to escalate their privileges.","status":"published","published":"2026-03-03T14:03:20Z","modified":"2026-06-25T13:32:31.694601001Z","updated_at":"2026-11-02T16:58:22.951676Z"}]}}