{"id":"CVE-2025-45006","aliases":["EUVD-2025-19672","GHSA-9mrj-rvvj-725q"],"status":"published","title":"Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb...","description":"Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.","severity":{"version":"3.1","score":9.1,"vector":"CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H","level":"critical","assessor":"adp","from":"cve"},"epss":{"day":"2026-11-10","score":0.00467,"percentile":0.40761,"model":"v2026.06.15"},"facts":{"in_kev":false,"known_exploited":false,"public_exploit":false,"fix_available":false},"cwes":["CWE-266"],"published":"2025-07-01T00:00:00Z","modified":"2026-06-17T09:25:20Z","references":[{"url":"https://github.com/chipsalliance/rocket-chip.git"},{"url":"https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications#ISA-Specifications"},{"url":"https://github.com/heyfenny/Vulnerability_disclosure/blob/main/RISCV/Rocket-chip/CVE-2025-45006/details.md"},{"url":"https://nvd.nist.gov/vuln/detail/CVE-2025-45006"},{"url":"https://github.com/advisories/GHSA-9mrj-rvvj-725q"}],"sources":{"cve":[{"id":"CVE-2025-45006","description":"Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.","status":"published","published":"2025-07-01T00:00:00Z","modified":"2025-07-02T13:58:38.672Z","cvss":[{"version":"3.1","score":9.1,"vector":"CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H","level":"critical","assessor":"adp"}],"cwes":["CWE-266"],"updated_at":"2026-11-02T14:32:36.385228Z"}],"euvd":[{"id":"EUVD-2025-19672","description":"Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.","status":"published","published":"2025-07-01T00:00:00Z","modified":"2025-07-02T13:58:38Z","cvss":[{"version":"3.1","score":9.1,"vector":"CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H","level":"critical"}],"updated_at":"2026-11-02T20:32:14.284181Z"}],"ghsa":[{"id":"GHSA-9mrj-rvvj-725q","title":"Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb...","description":"Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.","status":"published","published":"2025-07-01T21:32:26Z","modified":"2025-07-02T15:31:38Z","cvss":[{"version":"3.1","score":9.1,"vector":"CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H","level":"critical"}],"cwes":["CWE-266"],"updated_at":"2026-11-02T15:02:53.302581Z"}],"nvd":[{"id":"CVE-2025-45006","description":"Improper mstatus.SUM bit retention (non-zero) in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks.","status":"published","published":"2025-07-01T20:15:24.993Z","modified":"2026-06-17T09:25:20.007Z","cvss":[{"version":"3.1","score":9.1,"vector":"CVSS:3.1/AV:N/AC:L/PR:N/UI:N/S:U/C:H/I:N/A:H","level":"critical","assessor":"secondary"}],"cwes":["CWE-266"],"updated_at":"2026-11-02T14:11:15.754475Z"}]}}