{"id":"CVE-2025-54515","aliases":["EUVD-2025-198581","GHSA-hh36-fjhw-7fj3"],"status":"published","title":"The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors ...","description":"The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.","severity":{"version":"4.0","score":1,"vector":"CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:N","level":"low","assessor":"cna","from":"cve"},"epss":{"day":"2026-11-10","score":0.00133,"percentile":0.02904,"model":"v2026.06.15"},"facts":{"in_kev":false,"known_exploited":false,"public_exploit":false,"fix_available":false},"cwes":["CWE-1284"],"published":"2025-11-23T17:15:28Z","modified":"2026-10-18T20:10:00Z","products":[{"vendor":"amd","product":"alveo™ v80 compute accelerator"},{"vendor":"amd","product":"versal™  ai core series"},{"vendor":"amd","product":"versal™  ai edge series"},{"vendor":"amd","product":"versal™  hbm series"},{"vendor":"amd","product":"versal™  premium series"},{"vendor":"amd","product":"versal™  prime series"},{"vendor":"amd","product":"versal™  rf series"},{"vendor":"amd","product":"versal™ adaptive soc devices"}],"references":[{"url":"https://www.amd.com/en/resources/product-security/bulletin/amd-sb-8020.html"},{"url":"https://nvd.nist.gov/vuln/detail/CVE-2025-54515"},{"url":"https://github.com/advisories/GHSA-hh36-fjhw-7fj3"}],"sources":{"cve":[{"id":"CVE-2025-54515","description":"The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.","status":"published","published":"2025-11-23T17:15:28.948Z","modified":"2025-12-19T03:40:17.492Z","cvss":[{"version":"4.0","score":1,"vector":"CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:N","level":"low","assessor":"cna"}],"cwes":["CWE-1284"],"updated_at":"2026-11-02T14:32:27.603809Z"}],"euvd":[{"id":"EUVD-2025-198581","description":"The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.","status":"published","published":"2025-11-23T17:15:28Z","modified":"2025-12-19T03:40:17Z","cvss":[{"version":"4.0","score":1,"vector":"CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:N","level":"low"}],"updated_at":"2026-11-02T19:49:02.571203Z"}],"ghsa":[{"id":"GHSA-hh36-fjhw-7fj3","title":"The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors ...","description":"The Secure Flag passed to Versal™ Adaptive SoC’s Arm® Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.","status":"published","published":"2025-11-23T18:30:27Z","modified":"2025-11-23T18:30:37Z","cvss":[{"version":"4.0","score":1,"vector":"CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X","level":"low"}],"cwes":["CWE-1284"],"updated_at":"2026-11-02T15:04:55.324477Z"}],"nvd":[{"id":"CVE-2025-54515","description":"The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.","status":"published","published":"2025-11-23T18:15:55.163Z","modified":"2026-10-18T20:10:00.11Z","cvss":[{"version":"4.0","score":1,"vector":"CVSS:4.0/AV:L/AC:L/AT:P/PR:L/UI:A/VC:N/VI:N/VA:L/SC:N/SI:N/SA:N/E:X/CR:X/IR:X/AR:X/MAV:X/MAC:X/MAT:X/MPR:X/MUI:X/MVC:X/MVI:X/MVA:X/MSC:X/MSI:X/MSA:X/S:X/AU:X/R:X/V:X/RE:X/U:X","level":"low","assessor":"secondary"}],"cwes":["CWE-1284"],"updated_at":"2026-11-02T14:11:46.009629Z"}]}}