microcode_ctl vulnerabilities (AlmaLinux)
19 vulnerabilities.
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microcode_ctlAlmaLinux Improper handling of values for some Intel(R) Processors within Ring 0: Kernel, Hypervisor and... 4.5 Medium -
microcode_ctlAlmaLinux Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6... 7.0 High -
microcode_ctlAlmaLinux Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
microcode_ctlAlmaLinux Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
microcode_ctlAlmaLinux Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra... 6.8 Medium -
microcode_ctlAlmaLinux Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
microcode_ctlAlmaLinux Incorrect behavior order for some Intel(R) Core™ Ultra Processors may allow an unauthenticated... 4.1 Medium -
microcode_ctlAlmaLinux Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient... 5.7 Medium -
microcode_ctlAlmaLinux Improper input validation in UEFI firmware for some Intel(R) Processors may allow a privileged... 6.8 Medium -
microcode_ctlAlmaLinux Improper initialization in UEFI firmware OutOfBandXML module in some Intel(R) Processors may... 6.8 Medium -
microcode_ctlAlmaLinux Insufficient granularity of access control in UEFI firmware in some Intel(R) processors may allow... 6.8 Medium -
microcode_ctlAlmaLinux Hardware logic contains race conditions in some Intel(R) Processors may allow an authenticated... 2.8 Low -
microcode_ctlAlmaLinux Sequence of processor instructions leads to unexpected behavior in Intel(R) Core(TM) Ultra... 4.7 Medium -
microcode_ctlAlmaLinux Incorrect calculation in microcode keying mechanism for some Intel(R) Xeon(R) D Processors with... 5.3 Medium -
microcode_ctlAlmaLinux Protection mechanism failure of bus lock regulator for some Intel(R) Processors may allow an... 6.5 Medium -
microcode_ctlAlmaLinux Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors... 5.5 Medium -
microcode_ctlAlmaLinux Information exposure through microarchitectural state after transient execution from some... 6.5 Medium -
microcode_ctlAlmaLinux Protection mechanism failure in some 3rd and 4th Generation Intel(R) Xeon(R) Processors when... 6.1 Medium -
microcode_ctlAlmaLinux microcode_ctl bug fix and enhancement update No score