intel-ucode vulnerabilities (Alpine)
67 vulnerabilities.
-
intel-ucodeAlpine Exposure of sensitive information caused by incorrect data forwarding during transient execution... 4.0 Medium -
intel-ucodeAlpine Improper handling of values for some Intel(R) Processors within Ring 0: Kernel, Hypervisor and... 4.5 Medium -
intel-ucodeAlpine Improper handling of overlap between protected memory ranges in some microcode for some Intel(R)... 6.8 Medium -
intel-ucodeAlpine Improper access control for some Intel(R) Processors within Ring 3: User Applications may allow... 7.2 High -
intel-ucodeAlpine Always-incorrect control flow implementation in some firmware for some Intel(R) Xeon(R)... 4.5 Medium -
intel-ucodeAlpine Exposure of sensitive information caused by shared microarchitectural predictor state that... 6.8 Medium -
intel-ucodeAlpine Improper handling of values in the microcode flow for some Intel(R) Processor Family may allow an... 1.8 Low -
intel-ucodeAlpine Improperly implemented security check for standard in the DDRIO configuration for some Intel(R)... 4.5 Medium -
intel-ucodeAlpine Out-of-bounds write in the memory subsystem for some Intel(R) Xeon(R) 6 processors when using... 4.5 Medium -
intel-ucodeAlpine Insufficient control flow management in the Alias Checking Trusted Module (ACTM) firmware for... 7.0 High -
intel-ucodeAlpine Improper handling of overlap between protected memory ranges for some Intel(R) Xeon(R) 6... 7.0 High -
intel-ucodeAlpine Sequence of processor instructions leads to unexpected behavior for some Intel(R) Xeon(R) 6... 5.3 Medium -
intel-ucodeAlpine Insufficient granularity of access control in the OOB-MSM for some Intel(R) Xeon(R) 6 Scalable... 7.3 High -
intel-ucodeAlpine Missing reference to active allocated resource for some Intel(R) Xeon(R) processors may allow an... 4.1 Medium -
intel-ucodeAlpine Improper Isolation or Compartmentalization in the stream cache mechanism for some Intel(R)... 7.3 High -
intel-ucodeAlpine Improper buffer restrictions for some Intel(R) Xeon(R) Processor firmware with SGX enabled may... 7.0 High -
intel-ucodeAlpine Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
intel-ucodeAlpine Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
intel-ucodeAlpine Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra... 6.8 Medium -
intel-ucodeAlpine Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
intel-ucodeAlpine Insufficient resource pool in the core management mechanism for some Intel(R) Processors may... 5.7 Medium -
intel-ucodeAlpine Uncaught exception in the core management mechanism for some Intel(R) Processors may allow an... 6.8 Medium -
intel-ucodeAlpine Incorrect behavior order for some Intel(R) Core™ Ultra Processors may allow an unauthenticated... 4.1 Medium -
intel-ucodeAlpine Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient... 5.7 Medium -
intel-ucodeAlpine Improper input validation in UEFI firmware for some Intel(R) processors may allow a privileged... 8.7 High -
intel-ucodeAlpine Improper handling of physical or environmental conditions in some Intel(R) Processors may allow... 5.7 Medium -
intel-ucodeAlpine Sequence of processor instructions leads to unexpected behavior in the Intel(R) DSA V1.0 for some... 4.9 Medium -
intel-ucodeAlpine Improper access control in the EDECCSSA user leaf function for some Intel(R) Processors with... 6.8 Medium -
intel-ucodeAlpine Improper Finite State Machines (FSMs) in Hardware Logic for some Intel(R) Processors may allow... 5.6 Medium -
intel-ucodeAlpine Improper finite state machines (FSMs) in the hardware logic in some 4th and 5th Generation Intel... 5.7 Medium -
intel-ucodeAlpine Improper conditions check in some Intel(R) Xeon(R) processor memory controller configurations... 8.8 High -
intel-ucodeAlpine Improper finite state machines (FSMs) in hardware logic in some Intel(R) Processors may allow an... 5.6 Medium -
intel-ucodeAlpine Observable discrepancy in RAPL interface for some Intel(R) Processors may allow a privileged user... 6.8 Medium -
intel-ucodeAlpine Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may... 6.7 Medium -
intel-ucodeAlpine Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may... 6.9 Medium -
intel-ucodeAlpine Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM)... 7.3 High -
intel-ucodeAlpine Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated... 7.3 High -
intel-ucodeAlpine Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an... 7.3 High -
intel-ucodeAlpine Improper input validation in some Intel(R) TDX module software before version 1.5.05.46.698 may... 7.9 High -
intel-ucodeAlpine Hardware logic contains race conditions in some Intel(R) Processors may allow an authenticated... 2.8 Low -
intel-ucodeAlpine Sequence of processor instructions leads to unexpected behavior in Intel(R) Core(TM) Ultra... 4.7 Medium -
intel-ucodeAlpine Incorrect calculation in microcode keying mechanism for some Intel(R) Xeon(R) D Processors with... 5.3 Medium -
intel-ucodeAlpine Protection mechanism failure of bus lock regulator for some Intel(R) Processors may allow an... 6.5 Medium -
intel-ucodeAlpine Non-transparent sharing of return predictor targets between contexts in some Intel(R) Processors... 5.5 Medium -
intel-ucodeAlpine Information exposure through microarchitectural state after transient execution from some... 6.5 Medium -
intel-ucodeAlpine Protection mechanism failure in some 3rd and 4th Generation Intel(R) Xeon(R) Processors when... 6.1 Medium -
intel-ucodeAlpine Sequence of processor instructions leads to unexpected behavior for some Intel(R) Processors may... 8.8 High -
intel-ucodeAlpine Improper access control in some 3rd Generation Intel(R) Xeon(R) Scalable processors may allow a... 6.0 Medium -
intel-ucodeAlpine Unauthorized error injection in Intel(R) SGX or Intel(R) TDX for some Intel(R) Xeon(R) Processors... 7.2 High -
intel-ucodeAlpine Important: kernel security, bug fix, and enhancement update 6.5 Medium - Show olderLoading…