intel-microcode vulnerabilities (TuxCare)
53 vulnerabilities.
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intel-microcodeTuxCare Update of intel-microcode No score -
intel-microcodeTuxCare Update of intel-microcode No score -
intel-microcodeTuxCare Update of intel-microcode No score -
intel-microcodeTuxCare Update of intel-microcode No score -
intel-microcodeTuxCare Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
intel-microcodeTuxCare Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
intel-microcodeTuxCare Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra... 6.8 Medium -
intel-microcodeTuxCare Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
intel-microcodeTuxCare Insufficient resource pool in the core management mechanism for some Intel(R) Processors may... 5.7 Medium -
intel-microcodeTuxCare Uncaught exception in the core management mechanism for some Intel(R) Processors may allow an... 6.8 Medium -
intel-microcodeTuxCare Incorrect behavior order for some Intel(R) Core™ Ultra Processors may allow an unauthenticated... 4.1 Medium -
intel-microcodeTuxCare Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient... 5.7 Medium -
intel-microcodeTuxCare Insufficient granularity of access control in UEFI firmware in some Intel(R) processors may allow... 6.8 Medium -
intel-microcodeTuxCare Improper access control in the EDECCSSA user leaf function for some Intel(R) Processors with... 6.8 Medium -
intel-microcodeTuxCare Improper Finite State Machines (FSMs) in Hardware Logic for some Intel(R) Processors may allow... 5.6 Medium -
intel-microcodeTuxCare Improper finite state machines (FSMs) in the hardware logic in some 4th and 5th Generation Intel... 5.7 Medium -
intel-microcodeTuxCare Incorrect default permissions in some Intel(R) Xeon(R) processor memory controller configurations... 8.5 High -
intel-microcodeTuxCare Improper conditions check in some Intel(R) Xeon(R) processor memory controller configurations... 8.8 High -
intel-microcodeTuxCare Improper finite state machines (FSMs) in hardware logic in some Intel(R) Processors may allow an... 5.6 Medium -
intel-microcodeTuxCare Observable discrepancy in RAPL interface for some Intel(R) Processors may allow a privileged user... 6.8 Medium -
intel-microcodeTuxCare Mirrored regions with different values in 3rd Generation Intel(R) Xeon(R) Scalable Processors may... 6.7 Medium -
intel-microcodeTuxCare Protection mechanism failure in some 3rd, 4th, and 5th Generation Intel(R) Xeon(R) Processors may... 6.9 Medium -
intel-microcodeTuxCare Incorrect behavior order in transition between executive monitor and SMI transfer monitor (STM)... 7.3 High -
intel-microcodeTuxCare Improper isolation in some Intel(R) Processors stream cache mechanism may allow an authenticated... 7.3 High -
intel-microcodeTuxCare Improper isolation in the Intel(R) Core(TM) Ultra Processor stream cache mechanism may allow an... 7.3 High -
intel-microcodeTuxCare Update of alt-php No score -
intel-microcodeTuxCare Update of alt-php No score -
intel-microcodeTuxCare Sequence of processor instructions leads to unexpected behavior for some Intel(R) Processors may... 8.8 High -
intel-microcodeTuxCare Update of alt-php No score -
intel-microcodeTuxCare Update of alt-php No score -
intel-microcodeTuxCare Improper access control in some 3rd Generation Intel(R) Xeon(R) Scalable processors may allow a... 6.0 Medium -
intel-microcodeTuxCare Unauthorized error injection in Intel(R) SGX or Intel(R) TDX for some Intel(R) Xeon(R) Processors... 7.2 High -
intel-microcodeTuxCare Important: kernel security, bug fix, and enhancement update 6.5 Medium -
intel-microcodeTuxCare Improper isolation of shared resources in some Intel(R) Processors when using Intel(R) Software... 6.0 Medium -
intel-microcodeTuxCare Incorrect default permissions in some memory controller configurations for some Intel(R) Xeon(R)... 7.2 High -
intel-microcodeTuxCare Incorrect calculation in microcode keying mechanism for some 3rd Generation Intel(R) Xeon(R)... 6.1 Medium -
intel-microcodeTuxCare Insufficient granularity of access control in out-of-band management in some Intel(R) Atom and... 7.5 High -
intel-microcodeTuxCare CVE-2022-21233 does not affect BellSoft software 5.5 Medium -
intel-microcodeTuxCare Moderate: kernel-rt security and bug fix update 5.5 Medium -
intel-microcodeTuxCare Incomplete cleanup in specific special register read operations for some Intel(R) Processors may... 5.5 Medium -
intel-microcodeTuxCare Incomplete cleanup of microarchitectural fill buffers on some Intel(R) Processors may allow an... 5.5 Medium -
intel-microcodeTuxCare Incomplete cleanup of multi-core shared buffers for some Intel(R) Processors may allow an... 5.5 Medium -
intel-microcodeTuxCare Processor optimization removal or modification of security-critical code for some Intel(R)... 5.5 Medium -
intel-microcodeTuxCare Sensitive information accessible by physical probing of JTAG interface for some Intel(R)... 2.4 Low -
intel-microcodeTuxCare Improper access control for some 3rd Generation Intel(R) Xeon(R) Scalable Processors before BIOS... 5.5 Medium -
intel-microcodeTuxCare Out of bounds read under complex microarchitectural condition in memory subsystem for some Intel... 5.4 Medium -
intel-microcodeTuxCare Insufficient control flow management in some Intel(R) Processors may allow an authenticated user... 5.5 Medium -
intel-microcodeTuxCare Improper initialization of shared resources in some Intel(R) Processors may allow an... 5.5 Medium -
intel-microcodeTuxCare Hardware allows activation of test or debug logic at runtime for some Intel(R) processors which... 6.8 Medium -
intel-microcodeTuxCare Request a Quote < 2.3.9 - Admin+ Stored Cross-Site Scripting 4.8 Medium - Show olderLoading…