microcode_ctl vulnerabilities (TuxCare)
66 vulnerabilities.
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microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Improper handling of values for some Intel(R) Processors within Ring 0: Kernel, Hypervisor and... 4.5 Medium -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
microcode_ctlTuxCare Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
microcode_ctlTuxCare Incorrect initialization of resource in the branch prediction unit for some Intel(R) Core™ Ultra... 6.8 Medium -
microcode_ctlTuxCare Exposure of sensitive information caused by shared microarchitectural predictor state that... 5.7 Medium -
microcode_ctlTuxCare Insufficient resource pool in the core management mechanism for some Intel(R) Processors may... 5.7 Medium -
microcode_ctlTuxCare Uncaught exception in the core management mechanism for some Intel(R) Processors may allow an... 6.8 Medium -
microcode_ctlTuxCare Incorrect behavior order for some Intel(R) Core™ Ultra Processors may allow an unauthenticated... 4.1 Medium -
microcode_ctlTuxCare Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient... 5.7 Medium -
microcode_ctlTuxCare Improper input validation in UEFI firmware for some Intel(R) Processors may allow a privileged... 6.8 Medium -
microcode_ctlTuxCare Improper initialization in UEFI firmware OutOfBandXML module in some Intel(R) Processors may... 6.8 Medium -
microcode_ctlTuxCare Improper input validation in UEFI firmware for some Intel(R) Processors may allow a privileged... 8.7 High -
microcode_ctlTuxCare Improper input validation in UEFI firmware CseVariableStorageSmm for some Intel(R) Processors may... 8.7 High -
microcode_ctlTuxCare Improper input validation in XmlCli feature for UEFI firmware for some Intel(R) processors may... 8.7 High -
microcode_ctlTuxCare Improper input validation in UEFI firmware for some Intel(R) Processors may allow a privileged... 8.7 High -
microcode_ctlTuxCare Improper input validation in UEFI firmware for some Intel(R) processors may allow a privileged... 8.7 High -
microcode_ctlTuxCare Insufficient granularity of access control in UEFI firmware in some Intel(R) processors may allow... 6.8 Medium -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Improper validation in a model specific register (MSR) could allow a malicious program with ring0... 7.5 High -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score -
microcode_ctlTuxCare Update of microcode_ctl No score - Show olderLoading…